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Author: jackojacko Date: Jul 12, 2006 05:33
hi
> Are you aware that DRAM is going to be very slow for a cache? I don't
> know how much delay will be saved compared to external DRAM by not
> having to go off chip, but DRAM access times are on the order of 10's
> of nanoseconds, while most CPUs these days have internal memory cycle
> times of single digit nanoseconds. Normally cache memory is static ram
> which has a much larger area per bit. Of course if you are considering
> this as a level two cache, this might be very effective since you can
> load an entire word line at one time to your level one cache. In your
> example this could be 512 bits.
its level 2 as the level 1 is the 16 words of the write back que
DRAM speed depends on the charging of much capacitance, so smaller
arrays operate faster, but that, active columns thing, well could have
four of those maybe, would it speed up, yes, would it insert an extra
wait state unnecessarily at a lower speed , yes
umm?
cheers
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Author: Clever MonkeyClever Monkey Date: Jul 14, 2006 10:31
nosredna wrote:
[...]
> the modem. My questions: Do cable modems degrade over time or is this
> impossible because they're solid state?
Yes, they degrade. Even solid-state devices wear out, especially the
passive components which can be sensitive to environmental changes.
Some components near the signal or power supply voltages can simply wear
out.
I had a DSL modem fail in much the same way you describe: hard to
diagnose intermittent failures with periods of no problems at all.
Eventually those failures will become more and more common until keeping
the device connected is near impossible.
Certainly have your provider take their measurements at the the ground
block so you know you have sufficient signal to your demarcation point.
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Author: jackojacko Date: Jul 12, 2006 05:33
hi
> Are you aware that DRAM is going to be very slow for a cache? I don't
> know how much delay will be saved compared to external DRAM by not
> having to go off chip, but DRAM access times are on the order of 10's
> of nanoseconds, while most CPUs these days have internal memory cycle
> times of single digit nanoseconds. Normally cache memory is static ram
> which has a much larger area per bit. Of course if you are considering
> this as a level two cache, this might be very effective since you can
> load an entire word line at one time to your level one cache. In your
> example this could be 512 bits.
its level 2 as the level 1 is the 16 words of the write back que
DRAM speed depends on the charging of much capacitance, so smaller
arrays operate faster, but that, active columns thing, well could have
four of those maybe, would it speed up, yes, would it insert an extra
wait state unnecessarily at a lower speed , yes
umm?
cheers
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Date: Jul 17, 2006 06:36
On Sun, 16 Jul 2006 23:17:06 -0600, Michelle Steiner wrote
(in article news.west.cox.net>):
> In article <0001HW.C0E00C270003AAC8F0407530@ news.sasktel.net>,
> Ruddell canada.com> wrote:
> >>> It will upload only to a .mac account, but you can save the entire
>>> site to your disk and then use any FTP client to upload it.
>>
>> I'd have to upload it to the Mac account first before saving it or I
>> can put it together and save on my machine, then use an FTP client
>> for uploading to my current account?
>
> As I said, you can save it to your disk and then upload it to wherever
> you want.
Ok. That makes sense then and it looks good. I was watching a demo at one
of the local shops here but wasn't really able to ask any questions but from
what I did see, it sure looks slick...
--
Cheers!
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Author: Alex McDonaldAlex McDonald Date: Jul 12, 2006 07:50
rickman wrote:
> Alex McDonald wrote:
>> But in general, you're right; with the exception of she/he him/her
>> there's little indication as to gender in English.
>
> And has this limited our thinking about gender in any way???
No, I don't think I claimed that!
--
Regards
Alex McDonald
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Author: nosrednanosredna Date: Jul 17, 2006 10:50
In article news.isp.giganews.com>,
nosredna suscom.net> wrote:
> Except for a few ISP-related problems (including recent hardware
> upgrades that shut everyone down), my cable connection (Linksys
> EtherFast modem BEFCMU10 and Linksys router BEFSR11) has been flawless...
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| 1 Comment |
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Author: Clever MonkeyClever Monkey Date: Jul 17, 2006 11:27
nosredna wrote:
> In article news.isp.giganews.com>,
> nosredna suscom.net> wrote:
> >> Except for a few ISP-related problems (including recent hardware
>> upgrades that shut everyone down), my cable connection (Linksys
>> EtherFast modem BEFCMU10 and Linksys router BEFSR11) has been flawless
>> for the past year and a half. But yesterday I had several hours of no
>> connection. I did the usual resetting, rebooting, talked to tech
>> support, connected directly to modem w/o router, etc., but I still could
>> not connect. The ISP said there seemed to be nothing on their end
>> causing my problem, but they're sending a line tech out tomorrow to
>> check the cable coming in to the house. In the meantime I continued
>> troubleshooting on my end. Last night I was up and running again, even
>> with the router in the mix; this morning the connection was gone. I
>> disconnected the router, reset the modem, to no avail, and then two
>> hours later I was on again (w/o router). Last night I bought a new
>> Linksys modem, thinking that maybe my old one was dying, but now I'm
>> thinking I don't even need it. According to several usenet and Amazon
>> posts on this particular modem, version 2 (my old one) has been ...
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Author: jackojacko Date: Jul 12, 2006 05:33
hi
> Are you aware that DRAM is going to be very slow for a cache? I don't
> know how much delay will be saved compared to external DRAM by not
> having to go off chip, but DRAM access times are on the order of 10's
> of nanoseconds, while most CPUs these days have internal memory cycle
> times of single digit nanoseconds. Normally cache memory is static ram
> which has a much larger area per bit. Of course if you are considering
> this as a level two cache, this might be very effective since you can
> load an entire word line at one time to your level one cache. In your
> example this could be 512 bits.
its level 2 as the level 1 is the 16 words of the write back que
DRAM speed depends on the charging of much capacitance, so smaller
arrays operate faster, but that, active columns thing, well could have
four of those maybe, would it speed up, yes, would it insert an extra
wait state unnecessarily at a lower speed , yes
umm?
cheers
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Author: jackojacko Date: Jul 12, 2006 05:33
hi
> Are you aware that DRAM is going to be very slow for a cache? I don't
> know how much delay will be saved compared to external DRAM by not
> having to go offaster than stacks in memory.
And elsewhere in this thread you write, "Our goal is to make the hardware
and software smaller, cheaper, faster, and easier to program." I don't see
a conceptual foundation for the claim this hardware/software combination
is easier to program.
On the contrary I see no support for Forth's primary abstract data type:
the stack. Non-tail recursion will very quickly use up the six or so free
slots in "these kinds of stacks" before wrapping around and corrupting
data. If this hardware/software combination has no effective support for
non-tail recursion it will be less expressive and harder to program for
than hardware and software with support for large stacks.
So what is the abstract data type driving this programming model? If one
depends upon the semantics of pushing/popping a wrap-around bank of slots
then code will be tied to the specific number of slots implemented by the
hardware. Such code will break if the number of slots is ever increased,
and this is bound to occur in future revisions of hardware.
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