test

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I'm looking for more or less informations of the ISCAS 99 and 89
benchmarks.
Espacially I'm looking for a function description or model / draft of
the electric circuit or sth like that.
If anybody has some, could you please be so kind to post.
I need this for my practical semester where I write about reverse
engeniering of ic.
thanks
Marcus

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I have a strange trouble with a NetList Spice

The trouble is relative to vdd.

vdd 2000 0 dc 5

returns:

Node '2000' has only one component connected

Node 2000 is an input node for the subcircuit
MAIN PROJECT00_PRELAYOUT_01 1000 2000 3000 4000

Someone can help me ?

The NetList (generated by LasiCkt) is the following:

** SPICE Circuit File of PROJECT00_PRELAYOUT_01 - LasiCkt 7.0.3.0 03/31/08
10:27:00

* Start of L:\Lasi7\Project00_prelayout_01.hdr
.options reltol=.01 rshunt=1e9
.global vdd

vdd 2000 0 dc 5

cout 4000 0 500fF

vclkinput 1000 0 dc 0 pulse 0 5 0n 1n 1n 25ns 50ns

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What does some one mean when they say that the pins have tester
loading?
Also, I read something about funtional test, which that the test can
not be run at full speed, because of the tester loading on the other
pins.
your help will be greatly appreciated.

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FPGA/CPLD group on LinkedIn

http://www.linkedin.com/e/gis/56713/3CC3BF77FD22

Group for People Involved In the Design and Verification of FPGA's and
CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD
Design/Verification on your Profile to Join. (The focus is more on
FPGA/CPLD in the product as opposed to FPGA's solely as a path to an
ASIC)

Apologies for any multiple copies received. We would appreciate it if you
could distribute
the following call for papers to any relevant mailing lists you know of.

CALL FOR PAPERS
============================================================================
Special Session: Design, Testing and Formal Verification Techniques for
Integrated Circuits and Systems

DTVCS 2008

August 18-20, 2008 (Kailua-Kona, Hawaii, USA)
http://digilander.libero.it/systemcfl/dtvcs
=============================================================================

Special Session in the IASTED International Conference on Circuits and
Systems (CS 2008)
-------------------------------------------------------------------------------------------------------------------------------------
The IASTED International Conference on Circuits and Systems (CS 2008) will
take place in
Kailua-Kona, Hawaii, USA, August 18-20, 2008.
URL: http://www.iasted.org/conferences/cfp-625.html.