Charlie Springer wrote:

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Hardware uses similar protocol on both
CF and I.D.E. (HDD)

So , if you want a CF card 50 pin connector , i guess it
would be easy .

I have many tiny HDD boxes that have both
___44 pin IDE and ___CF 50. The PCB traces are shared .

Like DigiMates and X-drive 6230 .

So , assume CF copied ATA-IDE from the start ,,

Hardware wise , im excited about ARM7 on tiny PCB with
1MB SRAM and 32MB Flash , 144 pin CPU .
It can boot OpSys in 0.2 seconds , for the SRAM !
A color LCD later , not now .....
, but for now developement , i have

20 B.G. Micro ,, Dot_Matrix 128 by 64 B/W LCDs .
i will wire in 20 softkeys and be programming soon .

To start , it will take about 250KB to handle new HDD_F_S
to replace FAT32 and do b/w LCD .
F_S_ has a tiny Directory and no FAT tables , just
vectors inside each sector , that cross link sectors .
SRAM has a sector table .
some sectors are written double .
As new objects are written to disk , they may overwrite
these duplicates .
Objects are not deleted only marked and sometimes moved .

Small objects are never written contigous to the last object .
It would bunch , as W98 does , much work defrag' !!

In W95 , one could "files only" defrag !! it worked great !!
HDD cache is useful if power outage emergency .

But i will have SRAM ,so power out is not as bad .

M$ Vcache is malicious. If you nix it , WXP cant crash , but
run faster . But WXP will reinstall it !

I am the most clever hardware developer ever .
My H/W boots OpSys in 0.2 sec ,
Does not use English text .
Does not have Files/Folders ,
manages all objects auto ,
has MRU in all areas , its a hackers dream .
Multi-tasking does NOT allow Ints , but polls the top 2
and only when they are idle , does it poll the othes .

Since it executes stuff in perfect harmony , it gets
more work done , so it often vectors to low level stuff
just in time . After all programmer has to write tite
code , taking into consideration those top Prior's .

Consider the loss , when conventional kernels
are interupted , but to stack that Int , and finish the
more important Int because programmer did not
clear Ints in his lower thread ! ouch !!

My OpSys does not have that loss , its far more clever ..
There is one place in H/W PIC that is good.
PIC will rearrange Ints , if a low prior was first , but
a higher Prior' later went active .

But then my kernel calc's higher Context and thus
will never run a lower context , only to be snatched in middle by a
higher context .
It fully analysed that higher ,and
breaks between all the lower contexts threads , so
there is no loss at all .
----------Multi-Tasking------------------------
! Kernel polls DMA of the Highest_Contexts after ALL threads ..
I.E.
1) Higher_Context idles for 120 microsec ,
2) kernel starts Lower_Context threads .
as the 3rd thread of the Lower_Context ends .
3) kernel now finds Active_DMA Int , so .....
4) kernel swaps and runs the Higher_Context .
5) if and when Higher_Context idles , Lower_Context
can run its threads .