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Author: rickmanrickman Date: Jul 20, 2008 08:44
I have an application that would be well served by a small (or perhaps
"tiny" is the right word) CPU in an FPGA. The current design is
pushing 2000 LUTs and it is a 3000 LUT chip. The logic is mostly very
slow, so much of the current design could be done in the CPU allowing
much room for future expansion.
I asked in C.A.E and learned about the ZPU design which is open source
and GPL licensed. Oddly enough when I looked at it, it is a stack CPU
that is remarkably similar to one I designed some 6 years ago
specifically to run a forth like language as native machine code.
This one is smaller so it might well prefer it to my own. Also it is
supported by GCC.
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Author: Rod PembertonRod Pemberton Date: Jul 20, 2008 10:15
> I have an application that would be well served by a small (or perhaps
> "tiny" is the right word) CPU in an FPGA. The current design is
> pushing 2000 LUTs and it is a 3000 LUT chip. The logic is mostly very
> slow, so much of the current design could be done in the CPU allowing
> much room for future expansion.
>
"small cpu" and "slow". Here comes the obvious question... Something wrong
with 6502 or modern variants, Z80/Z80000, or older x86, ARM or the BASIC
Stamp (microcontroller w/BASIC interpreter)? Why are you designing your own
when so many cheap embedded market cpu solutions exist?
> I asked in C.A.E and learned about the ZPU design which is open source
> and GPL licensed. Oddly enough when I looked at it, it is a stack CPU
> that is remarkably similar to one I designed some 6 years ago
> specifically to run a forth like language as native machine code.
> This one is smaller so it might well prefer it to my own. Also it is
> supported by GCC.
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Author: rickmanrickman Date: Jul 20, 2008 18:29
On Jul 20, 1:15 pm, "Rod Pemberton" wrote:
>> I have an application that would be well served by a small (or perhaps
>> "tiny" is the right word) CPU in an FPGA. The current design is
>> pushing 2000 LUTs and it is a 3000 LUT chip. The logic is mostly very
>> slow, so much of the current design could be done in the CPU allowing
>> much room for future expansion.
>
> "small cpu" and "slow". Here comes the obvious question... Something wrong
> with 6502 or modern variants, Z80/Z80000, or older x86, ARM or the BASIC
> Stamp (microcontroller w/BASIC interpreter)? Why are you designing your own
> when so many cheap embedded market cpu...
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Author: jackojacko Date: Jul 21, 2008 05:33
> I asked in C.A.E and learned about the ZPU design which is open source
> and GPL licensed. Oddly enough when I looked at it, it is a stack CPU
> that is remarkably similar to one I designed some 6 years ago
> specifically to run a forth like language as native machine code.
> This one is smaller so it might well prefer it to my own. Also it is
> supported by GCC.
I am developing the indi core http://indi.hpsdr.com but at the moment
there are no tools, very low LUT count though. And do you include ROM
in this count? I am developing MID4th for mobile phones 16 bit ANS. I
intend to develop it further so that it may make ROM images for the
indi. I am sure the LUT count can be redued when VHDL specification is
used, but at present only a module based version exists.
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Author: Brad EckertBrad Eckert Date: Jul 21, 2008 07:29
On Jul 20, 8:44 am, rickman gmail.com> wrote:> I have an application that would be well served by a small (or perhaps
> "tiny" is the right word) CPU in an FPGA. The current design is
> pushing 2000 LUTs and it is a 3000 LUT chip. The logic is mostly very
> slow, so much of the current design could be done in the CPU allowing
> much room for future expansion.
>
> I asked in C.A.E and learned about the ZPU design which is open source
> and GPL licensed. Oddly enough when I looked at it, it is a stack CPU
> that is remarkably similar to one I designed some 6 years ago
> specifically to run a forth like language as native machine code.
> This one is smaller so it might well prefer it to my own. Also it is
> supported by GCC.
>
> To be honest, if I could use a core like this with a Forth development
> environment, I would prefer that. But I have yet to find Forth tools
> that even support arbitrary processors (ala GCC) much less provide a
> good debugging environment. I know the Forth philosophy seems to be
> that you can roll your own, but this is no small task if you want
> "good" tools. I remember Brad creating TinyBoot and ultimately ...
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Author: rickmanrickman Date: Jul 21, 2008 10:18
On Jul 21, 10:29 am, Brad Eckert tinyboot.com> wrote:> On Jul 20, 8:44 am, rickman gmail.com> wrote:
>
>
>>> I have an application that would be well served by a small (or perhaps
>> "tiny" is the right word) CPU in an FPGA. The current design is
>> pushing 2000 LUTs and it is a 3000 LUT chip. The logic is mostly very
>> slow, so much of the current design could be done in the CPU allowing
>> much room for future expansion.
>
>> I asked in C.A.E and learned about the ZPU design which is open source
>> and GPL licensed. Oddly enough when I looked at it, it is a stack CPU
>> that is remarkably similar to one I designed some 6 years ago
>> specifically to run a forth like language as native machine code.
>> This one is smaller so it might well prefer it to my own. Also it is
>> supported by GCC.
>
>> To be honest, if I could use a core like this with a Forth development
>> environment, I would prefer that. But I have yet to find Forth tools ...
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Author: jackojacko Date: Jul 21, 2008 11:01
Google MSL16 processor, vhdl available, forth like opcodes.
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Author: Bernd PaysanBernd Paysan Date: Jul 22, 2008 04:01
rickman wrote:
> I had looked at the B16 a long time ago and didn't think it was really
> suitable for an FPGA internal core. I want to say it is designed for
> a 16 bit external RAM rather than internal memory. I also don't know
> that there are any tools available for it. Has anyone else ended up
> using it?
You can't have looked at the b16 I've loaded up. It uses an internal RAM,
but can also use an external one (the internal RAM of small FPGAs is often
small). Anyway, it's a *core*, it's up to you to connect it.
There's an assembler, simulator, and a small bootloader available for it,
it's part of the distribution. You might have missed it, because it's only
a few hundred lines long ;-).
We had a student who build a proof-of-the-concept C compiler with an old
stack-based compiler kit (was easier to do than with GCC), but it's not
ready for use.
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Author: rickmanrickman Date: Jul 22, 2008 06:36
On Jul 22, 7:01 am, Bernd Paysan wrote:
> rickman wrote:
>> I had looked at the B16 a long time ago and didn't think it was really
>> suitable for an FPGA internal core. I want to say it is designed for
>> a 16 bit external RAM rather than internal memory. I also don't know
>> that there are any tools available for it. Has anyone else ended up
>> using it?
>
> You can't have looked at the b16 I've loaded up. It uses an internal RAM,
> but can also use an external one (the internal RAM of small FPGAs is often
> small). Anyway, it's a *core*, it's up to you to connect it.
Sorry, I was working from memory. I looked at the docs and it would
seem that I was remembering some other CPU. The B16 is a like my CPU
in using dual stacks. But I don't see any real advantages. The size
is about the same (600 LUTs) and that number does not include
interfacing which mine does. It also seems to run a bit slow, but
that may be more a function of the chip used rather than design.
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Author: Bernd PaysanBernd Paysan Date: Jul 22, 2008 09:40
rickman wrote:
> Sorry, I was working from memory. I looked at the docs and it would
> seem that I was remembering some other CPU. The B16 is a like my CPU
> in using dual stacks. But I don't see any real advantages. The size
> is about the same (600 LUTs) and that number does not include
> interfacing which mine does. It also seems to run a bit slow, but
> that may be more a function of the chip used rather than design.
Altera or Xilinx LUTs? My number are Altera LUTs, which have about half the
capability of Xilinx, and it was the "large" version. The chip was quite
slow, indeed; the b16 runs between 250 and 500MHz in 0.18µ (real
TSMC-compatible silicon, standard gates), depending on which version you
use (small=slow, large=faster).
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