I've done some googling on intellasys discussions here (but really can't
devote much time to that because of sickness, pity there isn't summaries
in newsgroups or threads). I've seen discussions where people suggest
that Intellasys are after Arm like contracts. But what is the real target?

The Arm field is populated by ready made solutions with reference designs,
and software to run on them. If we look at it on multiple levels, the
present chip doesn't seem to be targeted at the same...

On Fri, 23 May 2008 06:58:43 +1000, Wayne
optusnet.com.au>

Something I forgot, is about the future of design, which is directly of
interest to anybody that uses these devices, or even pics. I would like
to see a full speed general purpose embedded serial...

On May 24, 2:26 pm, Wayne optusnet.com.au>
wrote:

Winbond's 25Q 8-pin serial flash parts can shift out data at 320M bps
using quad-data-rate mode at 80MHz. The cool thing is that they are
backward compatible with industry standard serial flash chips. I
suspect other serial flash vendors will eventually offer parts with
high speed modes, because even serially, code can be executed in place
faster than using parallel flash.

I think you need to get your hands on a Xilinx or Altera evaluation
board and start designing your own hardware as a way to address all of
these ideas in your head.

As for Intellasys, the most important thing may be the patents it
spawns. Chuck tends to be way ahead of his time, so ten years from now
when the big companies are doing sea-of-processors, the lawyers will
once again start pulling rabbits out of their hats.

Hmm, thanks for that. Now to interface it to the seaforth bi levels. But
I would still need write performance and durability, however, it is a good
find for execution.

On Wed, 28 May 2008 01:46:14 +1000, Brad Eckert
tinyboot.com> wrote:

Well, if I could do it myself, I would be keeping it to myself ;) and not
be telling other people about it :). However, I was hoping that the
seaforth would prove to be a viable lower power way to model these things
then to go to the FPGA learning curve.

On May 29, 2:43 am, Wayne optusnet.com.au>
wrote:

They have their work cut out for them. SeaForth is so different that
they have to make all new tools from scratch. They're inventing a
design flow to go with their chips. Their users have to learn a new
way to build applications.

On May 29, 2:43 am, Wayne optusnet.com.au>
wrote:

Considering that a 256Mbit DRAM goes for about $4.00 these days,
suppose you want a sea-of-processors chip with about the same die
size. If you use half the die area for RAM and half for CPU and
interconnect, that's 128M RAM bits, and if each CPU core gets 10K bits
(like a C18 core's RAM), there would be 1000 processor cores on the
chip. By the time sea-of-asynchronous-processors catches on, smaller
process nodes will be available so it would be reasonable to assume
that it will be possible to put 4096 processors on a low-cost chip. If
you allow 4W of power dissipation, each core would have to average
1mW. Asynchronous processors like the C18 are the best bet for
achieving this.

Hmm. I was wrong about that Ambarella chip, it's average power
requirements are more than I thought. I also tried looking for the
article that I read that went into the internal processor array, but can't
find it now.

On Fri, 30 May 2008 04:46:04 +1000, Brad Eckert
tinyboot.com> wrote:

Brad Eckert tinyboot.com> writes:

The problem with that concept is that DRAM processes are not very good
for CPUs and vice versa; also, CPUs tend to use many more layers,
which increases production cost.

On Mon, 02 Jun 2008 05:12:43 +1000, Anton Ertl
mips.complang.tuwien.ac.at> wrote:

I think that was the whole purpose, to get the batch numbers up.

Yes, but I would like at least one full speed 18 bit execution address
space internally or externally, and use it as a general purpose device as
well.

Wayne wrote:

They would indisputably love to be producing in volume. It will take a
while to get customers to that state, however.