hi

fixed the FI bug (post increment double mux with (Q) ho-hum. Reduced
some of the inferred latches. Still have to optimize ALU. Cosidering
that 3 33 bit latches are infered for alu intermediates, which are
only used in alu instructions (don't know why i'd want them infrred to
carry data between independent alu ops, but thats VHDL for ya.)

I hope to get it into the 300s, and get the Fmax above the currnt
49MHz (in C3 speed grade MAX II). (16 -bit version, but fully generic)

At single cycle per instruction execute + 1 cycle fetch, with delayed
synchronous read, => about 25 MIPS) This will have to be halved for 8
bit memory data interface.

I will make a half width bus interface unit later, and supply VHDL for
DAC and PIO mode 4 HD controller too.

cheers
jacko.

hi

Optimized a bit, now at 301 LEs, must find out how to specify carry
routing in vhdl, as I wrote the adder code using xor and and. Fixed a
bug which saved wrong return address.

cheers
jacko