Re: Compiler ordering barriers in C++0x

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Re: Compiler ordering barriers in C++0x

Group: comp.lang.c++.moderated · Group Profile
Author: Anthony Williams
Date: May 3, 2008 14:21

"Dmitriy V'jukov" gmail.com> writes:

> On 2 Ð¼Ð°Ð¹, 14:43, Anthony Williams yahoo.com> wrote:
> I can prove that I have happens-before relation if I can enforce
> correct compiler ordering. Consider following code:
>
> std::vector g_nonatomic_user_data;
> std::atomic_int g_atomic1;
> std::atomic_int g_atomic2;
>
> std::vector thread()
> {
> g_atomic1.store(1, std::memory_order_relaxed);
> // compiler store-load fence
> if (g_atomic2.load(std::memory_order_relaxed))
> {
> g_atomic1.store(0, std::memory_order_relaxed);
> return std::vector();
> }
> // compiler acquire fence
> std::vector local = g_nonatomic_user_data;
> // compiler release fence
> g_atomic1.store(0, std::memory_order_relaxed);
> return local;
> }
>
> It's a kind of Peterson's algorithm *but* w/o store-load memory
> barrier, and w/o acquire and release barriers. The point is that I
> still can prove happens-before relation wrt accesses to
> g_nonatomic_user_data, if I can enforce mentioned compiler barriers.
> Basically I need to ensure that accesses to g_nonatomic_user_data will
> not hoist above or sink below accesses to g_atomic1 in generated
> machine code.
> Now I can do this with _ReadWriteBarrier (msvc) or "__asm__
> __volatile__ ("" : : :"memory")" (gcc).

You're using relaxed atomics. This is dangerous. In particular, relaxed
atomics do NOT provide happens-before relations between threads. In
particular, the relaxed load of g_atomic2 doesn't give you any guarantee about
the state of g_nonatomic_user_data.

Anthony
--
Anthony Williams | Just Software Solutions Ltd
Custom Software Development | http://www.justsoftwaresolutions.co.uk
Registered in England, Company Number 5478976.
Registered Office: 15 Carrallack Mews, St Just, Cornwall, TR19 7UL

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