> Will it be possible to issue only compiler ordering barrier (release,
> acquire or full), but not hardware ordering barrier in C++0x?
>
> Accesses to volatile variables are ordered only with respect to
> accesses to other volatile variables. What I want it to order access
> to variable with respect to accesses to all other volatile and non-
> volatile variables (w/o any hardware barriers, only compiler
> ordering).
>
> Now it can be accomplished with "__asm__ __volatile__
> ("" : : :"memory")" on gcc, and with _ReadWriteBarrier() on msvc. I am
> interested whether it will be possible to do this in C++0x language w/
> o compiler dependency.
>
> Such compiler barriers are useful in effective synchronization
> algorithms like SMR+RCU:http://sourceforge.net/project/showfiles.php?group_id=127837
> (fastsmr package)
> because they allows one to eliminate all hardware memory barriers from
> fast-path.
>
> Dmitriy V'jukov
>