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Big Endian, Little Endian.         


Author: Le Chaud Lapin
Date: May 9, 2008 19:31

Hi All,

What header or compile-time trick allows one to determine the byte-
order of target CPU?

TIA,

-Le Chaud Lapin-

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13 Comments
Re: Big Endian, Little Endian.         


Author: Sohail Somani
Date: May 10, 2008 04:20

Le Chaud Lapin wrote:
> Hi All,
>
> What header or compile-time trick allows one to determine the byte-
> order of target CPU?

AFAIK, you should use predefined macros like the ones here:

http://predef.sourceforge.net/prearch.html

There are runtime tricks but that is pretty silly unless you are using
an autoconf like thing in your build system to determine endianness.

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Re: Big Endian, Little Endian.         


Author: clemd
Date: May 10, 2008 04:21

On May 9, 8:25 pm, Le Chaud Lapin gmail.com> wrote:
> Hi All,
>
> What header or compile-time trick allows one to determine the byte-
> order of target CPU?

Not possible. Depending on the CPU and the memory system, the byte
order may be dynamic, or it may vary among sections of memory. Or it
may be "mixed endian" (not strictly big or little), or have no
endianness.

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Re: Big Endian, Little Endian.         


Author: Sohail Somani
Date: May 10, 2008 13:08

clemd@acm.org wrote:
> On May 9, 8:25 pm, Le Chaud Lapin gmail.com> wrote:
>> Hi All,
>>
>> What header or compile-time trick allows one to determine the byte-
>> order of target CPU?
>
> Not possible. Depending on the CPU and the memory system, the byte
> order may be dynamic, or it may vary among sections of memory. Or it
> may be "mixed endian" (not strictly big or little), or have no
> endianness.

Wow. Do you have an example?

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Re: Big Endian, Little Endian.         


Author: Bo Persson
Date: May 11, 2008 07:52

Sohail Somani wrote:
> clemd@acm.org wrote:
>> On May 9, 8:25 pm, Le Chaud Lapin gmail.com> wrote:
>>> Hi All,
>>>
>>> What header or compile-time trick allows one to determine the
>>> byte- order of target CPU?
>>
>> Not possible. Depending on the CPU and the memory system, the byte
>> order may be dynamic, or it may vary among sections of memory. Or
>> it may be "mixed endian" (not strictly big or little), or have no
>> endianness.
>
> Wow. Do you have an example?

You will find that some hardware is switchable, or that the endianness
of integers and floats are not the same, or that the endianness is not
at the byte level. :-)

http://en.wikipedia.org/wiki/Endianness

Bo Persson
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Re: Big Endian, Little Endian.         


Author: Jonathan Thornburg [remove -animal to reply]
Date: May 11, 2008 07:52

clemd@acm.org wrote:
> Not possible. Depending on the CPU and the memory system, the byte
> order may be dynamic, or it may vary among sections of memory. Or it
> may be "mixed endian" (not strictly big or little), or have no
> endianness.

Sohail Somani taggedtype.net> wrote:
> Wow. Do you have an example?

The Digital PDP-11 and VAX systems (= arguably the most popular and
influential minicomputers in the world for the 1960s-70s and 70s-80s
respectively) were little-endian for integers, but stored floating-point
numbers in memory in a mixed-endian order. A floating-point number
(either IEEE or one of the VAX-only formats) which might be the register
bit-pattern 0x87654321 would be stored in memory with bytes in the order
(if my slight dim memories haven't faded too badly) first 2, then 1, 4,
3, 6, 5, 8, and finally 7. The reasons for this go back to backwards
compatability with early PDP-11 systems with had 16-bit memory buses.
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Re: Big Endian, Little Endian.         


Author: clemd
Date: May 13, 2008 10:07

On May 10, 1:08 pm, Sohail Somani taggedtype.net> wrote:
> cl...@acm.org wrote:
>> On May 9, 8:25 pm, Le Chaud Lapin gmail.com> wrote:
>>> Hi All,
>
>>> What header or compile-time trick allows one to determine the byte-
>>> order of target CPU?
>
>> Not possible. Depending on the CPU and the memory system, the byte
>> order may be dynamic, or it may vary among sections of memory. Or it
>> may be "mixed endian" (not strictly big or little), or have no
>> endianness.
>
> Wow. Do you have an example?

Dynamic: HP PA/RISC can switch endianness dynamically.

Vary among sections of memory: in the Intel i960CA, the endianness of
16 memory sections were individually selectable. I don't remember
whether they were dynamic.
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Re: Big Endian, Little Endian.         


Author: Ronald Natalie
Date: May 13, 2008 19:10

clemd@acm.org wrote:
> On May 10, 1:08 pm, Sohail Somani taggedtype.net> wrote:
>> cl...@acm.org wrote:
>>> On May 9, 8:25 pm, Le Chaud Lapin gmail.com> wrote:
>>>> Hi All,
>>>> What header or compile-time trick allows one to determine the byte-
>>>> order of target CPU?
>>> Not possible. Depending on the CPU and the memory system, the byte
>>> order may be dynamic, or it may vary among sections of memory. Or it
>>> may be "mixed endian" (not strictly big or little), or have no
>>> endianness.
>> Wow. Do you have an example?
>
> Dynamic: HP PA/RISC can switch endianness dynamically.

The MIPS chip that was in the SGI's and DEC pre-Alphas among others
could be switched. We referred to the DEC version as the SPIM.

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Re: Big Endian, Little Endian.         


Author: Andy Champ
Date: May 13, 2008 19:10

clemd@acm.org wrote:
> No endianness: I don't have an example, but if all primitive datatypes
> have the same size there will be no endianness. In C99 that would mean
> that CHAR_BIT == 64 or more, so that the minimum size long long fits
> into a single character.


Correct me if I'm wrong, but doesn't the standard just say sizeof(int)
>= sizeof char; sizeof(long) >= sizeof(int); etc - so there's no
guarantee that a long long is any particular size...

Andy

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Re: Big Endian, Little Endian.         


Author: Carl Barron
Date: May 13, 2008 19:20

In article
u12g2000prd.googlegroups.com>,
<"clemd@acm.org"> wrote:
> Mixed endian: other posters have already mentioned the beloved PDP-11.
> In addition to floating point being mixed endian, I recall that long
> (32-bit) was also. But that was by software convention; I don't
> remember any hardware support for 32-bit integers.
>
> No endianness: I don't have an example, but if all primitive datatypes
> have the same size there will be no endianness. In C99 that would mean
> that CHAR_BIT == 64 or more, so that the minimum size long long fits
> into a single character.

Might be off topic, but where does c99 state range of long long
larger than range of int? My reading of the c99 standard states the
same thing as c89 and hence c++98 [and probably later revisions]
regarding sizeof various signed integral types. That is sizeof(X) ==
1 for any integral type X, is legal.
So that if the machine is a 'natural' 32 bit word machine, then
CHAR_BIT == 32 is legal.
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