I am trying to extract the coupling capacitance and hence estimate
the cross talk noise. I know that by running Fire-n-Ice on the placed
and routed DEF file I can extract the SPEF and I have read that you
could write a perl script to process this SPEF file and get the
coupling cap for a certain number of aggressor nets. Does anybody have
any such script that I could borrow? Or perhaps some pointers where I
can obtain this. I will really appreciate any kind of help.
As you all know, the 22nd conference on VLSI Design would be held in
New Delhi from January 5 to 9th 2009 at The Hotel Taj Palace. The
theme for the conference is "Improving Productivity through higher
abstractions".
We would like to whole-heartedly welcome you to Delhi in Jauary 2009
to be part of this mega annual event and encourage your participation
as an author for papers, tutotials etc. and/or in the Design Contest
and/or the newly announced "EDA Software Contest". Details are
available on the website:
Joining will allow you to find and contact other FPGA, CPLD members on
LinkedIn. The goal of this group is to help members:
-> Reach other members of FPGA & CPLD community
-> Accelerate careers/business through referrals from FPGA Group
members
-> Know more than a name – view rich professional profiles from fellow
FPGA Group members
Here’s the link to join:
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On her Standards Game Blog today, Karen Bartleson announced that
Accellera formed a subcommittee to define a standard for verification
interoperability.
That is, Synopsys is stepping up to an industry leadership position to
settle the VMM / OVM war.
This is the right move to do this in Accellera because it gives us
input into the process, rather than just the EDA vendors controlling
the process for their own benefit. Karen points out in her blog that
it was user pressure they heard that made them open up VMM. That's
us!
If you want to get your copy of the open VMM code that the new
Accellera working group will use you will need to wait until they get
the working group web landing page created. Karen did not say who
would chair the group, but if you want her to pass your name on to the
new chair, you can email her at karenb @ synopsys . com.
Bit-Precise Reasoning is increasingly being used for the analysis of
many real world hardware and software systems. Current applications
include microcode validation, word-level model checking, software
verification, equivalence checking, and random testcase generation.
The continued success in these and other applications depends on the
development of more efficient decision procedures for bit-precise
reasoning, their combination with decision procedures for other
theories (e.g. the theory of arrays), as well as domain-specific
techniques to further increase the scalability of the analysis.
The goal of this workshop is to bring together researchers in
Bit-Precise Reasoning with industrial users. Topics of interest
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