Some time ago, I believe it was on this newsgroup, someone mentioned
the forthcoming ATI FireStream 9170 floating-point coprocessor card.

Although I visit the Tom's Hardware site occasionally, I missed this
article until I saw a link to it on HPCwire:

http://www.tgdaily.com/content/view/39348/135/1/1/

This is the second page of the article; it compares other coprocessor
products available now.

Two items, in the $500 range, are high-end video cards, one from AMD/
ATI and the other from Nvidia. They can be used with the same software
from these companies as their coprocessor cards can be used with.
According to the article, the Nvidia Tesla coprocessor card basically
uses the same components as the video card, but costs twice as much
because it's a less mass-market item - omitting the video components
lets the card run at a slightly higher speed.

This sounded so peachy keen that I wanted to run out and buy one
*right now*!

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ISNN2009 CALL FOR PAPERS

The Sixth International Symposium on Neural Networks (ISNN 2009) will
be held in Wuhan,
following the successes of previous events. Composed of three parts
(Wuchang, Hankou, and Hanyang), Wuhan is the...

On Sep 12, 4:22 am, Elcaro Nosille akapost.com> wrote:

Let me preface this by indication I know nothing in particular about
Intel manufacturing.

However, at several companies I worked at over the last 25 years, the
company would test parts and then assign them market bins. A market
bin was a 2 dimensional bin with max frequency range on one axis and
max power consumption on the other axis. From this set of bins, one
could pick parts and assemble these into a large number of offerings.

We would see chips from the same wafer that would go in the high
frequecy and high power bins and other chips from the same wafer go
into lower frequency and lower power bins. You don't have to get to
the mask revision level (or process tweeks) to see these effects.

Thus, it is highly likely that multiple CPUs from the same stepping
and targeted towards the same frequency range could differ in their
sensitivity to voltage and frequencies.

Hi,
Project underway; "Co-Operative Assembly"

Using the internet for people to gather and form informational organizations
(and communities), implementing and enforcing public checks and balances, by
way of three internal branches of information processing, ID verification,
randomized task distribution, and a variety of other mechanisms.

The software involves a heavyweight file system (SiteFS), and transport
infrastructure for groups (GroupBus), and more, all presently in design.
This is a public project.

Blog: http://coopassembly.blogspot.com/
Discussion: http://groups.google.com/group/coopassembly

Sincerely,
Mark G. Meyers

Hi,
Project underway; "Co-Operative Assembly"

Using the internet for people to gather and form informational organizations
(and communities), implementing and enforcing public checks and balances, by
way of three internal branches of information processing, and a variety of
other mechanisms.

The software involves a heavyweight file system (SiteFS), and transport
infrastructure for groups (GroupBus), and more, all presently in design.
This is a public project.

Blog: http://coopassembly.blogspot.com/
Discussion: http://groups.google.com/group/coopassembly

Sincerely,
Mark G. Meyers

Hi,
I'm just starting to let folks know, today, that I'm starting to make links
and sites public, for the Co-Operative Assembly (that I've been sitting on
for bit).

Well, this is a nice announcement. It seems to me that the 4th House, or the
press and the media, has been hijacked, and people need some kind of
infrastructure to get their freedom of information back.

Enter the Co-Operative Assembly, an organization that people create, with 3
internal branches of information processing, with verified identities for
all work performed, and with other checks, such as a complete set of public
records to back up any public, informational product. The purpose of this
design is to give people the infrastructure they need, and the ability to
gain trust in the public eye. Even to the point of organizations endorsed by
reputable sources as useful for research purposes.

Modern technology gives us the ability to enforce checks and balances our
forefathers never would have considered.

Blog: http://coopassembly.blogspot.com/
Discussions: http://groups.google.com/group/coopassembly

http://www.cilk.com/resources-for-multicoders/for-developers-only/

(For GCC and Visual Studio)

documentation, code samples, training materials for developers

Cilk++ ships in several months, but the above is a preview of what's coming.

David Wang (see quote below) described a way to get chipkill
protection with x8 memory chips using a 144 pin data bus. Wang's
emphasis was on minimizing the number of data pins required, but I
want to minimize the number of chips required, regardless of the width
of the data bus. The standard way to get chipkill protection is with
36 x4 chips. Is Wang describing an 18 x8 chip configuration, or 36 x8?
Does his system actually provide SSC/DSD, or just SSC/DED?
The standard 36 x4 configuration has 1/9 memory capacity overhead (it
uses 8/9 of the memory for data, and 1/9 for ECC). Is it possible in
any way to get chipkill protection using less than 36 chips without
requiring more than 1/9 overhead?
Another obvious way to get full SSC/DSD protection is with a 3 x64 (or
3 x128, or any other data...