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Author: karthikbalagurukarthikbalaguru Date: May 14, 2008 13:36
Hi,
What could be the best method to achieve zero latency context switch
between
two processes ?
Thx in advans,
Karthik Balaguru
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Author: Andrew SmallshawAndrew Smallshaw Date: May 14, 2008 14:04
On 2008-05-14, karthikbalaguru gmail.com> wrote:>
> What could be the best method to achieve zero latency context switch
> between
> two processes ?
Two processors, running each process in parallel. There's _always_
some latency when performing a context switch. The absolute minimum
would be a single clock cycle but that isn't instantaneous.
Interrupts aren't instant for this very reason.
So, time to modify the question. What's the maximum latency that
would be acceptable? You can work backwards from that.
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Author: N1N1 Date: May 14, 2008 14:10
Ammiravo la mia cresta allo specchio quando karthikbalaguru
gmail.com> ha detto :
> Hi,
>
> What could be the best method to achieve zero latency context switch
> between
> two processes ?
>
As Andrew Smallshaw just said it's not possible to have zero latency in a
context switch. The best option at all would be to have more than a group
of registers so that all you have to do is to "point" the CPU to the one
you want to use with no need of moving data from regs to memory and
viceversa.
--
Nuno on zx-6r '04 & CR 250 '98 working in progress...
Say you, say me...say 'na mignotta!
*** www.gladio.org ***
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Author: Ed ProchakEd Prochak Date: May 14, 2008 17:23
On May 14, 4:36 pm, karthikbalaguru gmail.com>
wrote:> Hi,
>
> What could be the best method to achieve zero latency context switch
> between
> two processes ?
>
> Thx in advans,
> Karthik Balaguru
Dual processors, dual RAM banks, Dual peripherals.
Ed
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Author: Paul KeinanenPaul Keinanen Date: May 14, 2008 20:03
On Wed, 14 May 2008 21:10:43 GMT, N1 wrote:
>Ammiravo la mia cresta allo specchio quando karthikbalaguru
> gmail.com> ha detto :
>>> Hi,
>>
>> What could be the best method to achieve zero latency context switch
>> between
>> two processes ?
>>
>
>As Andrew Smallshaw just said it's not possible to have zero latency in a
>context switch. The best option at all would be to have more than a group
>of registers so that all you have to do is to "point" the CPU to the one
>you want to use with no need of moving data from regs to memory and
>viceversa.
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Author: CBFalconerCBFalconer Date: May 14, 2008 21:44
Paul Keinanen wrote:
> N1 wrote:
>> gmail.com> ha detto :
>>>>> What could be the best method to achieve zero latency context
>>> switch between two processes ?
>>
>> As Andrew Smallshaw just said it's not possible to have zero
>> latency in a context switch. The best option at all would be to
>> have more than a group of registers so that all you have to do
>> is to "point" the CPU to the one you want to use with no need of
>> moving data from regs to memory and viceversa.
>
> This was exactly how it was done in the Texas TMS9900 processor
> with the register set in RAM. Unfortunately this was done in an
> era, when microprocessors did not have a fast cache, so the
> penalty during normal operation was severe, but the context
> switch was fast :-).
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Author: Bill LearyBill Leary Date: May 14, 2008 22:49
"CBFalconer" yahoo.com> wrote in message
news:482BBFBC.71A71101@yahoo.com...> Remember the Z80? One instruction flipped you to the
> alternate register set (ABCDEHL).
Two instructions.
08 EX AF,AF' ; AF <-> AF'
D9 EXX ; BC/DE/HL <-> BC'/DE'/HL'
- Bill
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Author: Frank BussFrank Buss Date: May 15, 2008 10:44
karthikbalaguru wrote:
> What could be the best method to achieve zero latency context switch
> between two processes ?
As you can see from the other answers, this depends largely on the CPU you
are using. One exception is a simple Forth system, e.g. a threaded code
implementation ( http://www.complang.tuwien.ac.at/forth/threaded-code.html
). Instead of using interrupts, which can have large latencies because of
instruction cache flush etc., you could simply execute 100 instructions for
each process. Process switching could be done by loading a new instruction
pointer for the threaded code and stack pointer. This will be fast on every
CPU.
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Author: Paul KeinanenPaul Keinanen Date: May 15, 2008 11:34
On Thu, 15 May 2008 00:44:44 -0400, CBFalconer yahoo.com>
wrote:
>Paul Keinanen wrote:
>> N1 wrote:
>>> gmail.com> ha detto :
>>>>>>> What could be the best method to achieve zero latency context
>>>> switch between two processes ?
>>...
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Author: Stefan CarterStefan Carter Date: May 15, 2008 12:30
>>Remember the Z80? One instruction flipped you to the alternate
>>register set (ABCDEHL). IX, IY, SP and PC were unchanged. You had
>>to be sure no idiot used the alternates in the bios, however.
>
> Perfectly fine, if you only had some miniature system with just two
> tasks :-).
Which is why ZiLOG opted for a different approach for their Z8
microcontroller - a register pointer, selecting one of the many working
register groups in the vast register file (at least, not external RAM like
in the TI's case).
Fast context switch and awkward program design :(
Stefan
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